Course: SystemVerilog Assertions & Functional Coverage FROM SCRATCH

SystemVerilog Assertions & Functional Coverage FROM SCRATCH

  • Life Time Access
  • Certificate on Completion
  • Access on Android and iOS App
  • Self-Paced
About this Course

SystemVerilog Assertions and Functional Coverage is a comprehensive from-scratch course on Assertions and Functional Coverage that covers features of SV LRM 2005/2009 and 2012. The course does not require any prior knowledge of OOP or UVM. The course is taught by a 30 year veteran in the design of CPU and SoC who published a book on SVA and FC in 2014 and hold 13 U.S. patents on design verification. The course has 33 lectures and is 8.5 hours in length (with lifetime access) that will take you step by step through learning of the languages.

The knowledge gained from this course will help you find and cover those critical and hard to find and cover design bugs. SystemVerilog Assertions and Functional Coverage are very important parts of overall functional verification methodology and all verification engineers need this knowledge to be successful. The knowledge of SVA and FC will indeed be highlights of your resume when seeking a challenging job or project The course offers step-by-step guide to learning of SVA and FC with plenty of real life applications to help you apply SVA and FC to your project in shortest possible time. SVA and FC helps critical aspect of Functional/Temporal domain coverage which is simply not possible with code coverage.

Who is the target audience?

  • Hardware Design and Verification Engineers
  • New college graduates who are entering VLSI design and verification field
  • EDA Application Engineers and Consultants
  • Verification IP developers
Basic knowledge
  • Basic knowledge of Verilog
  • Basic knowledge of hardware design and verification
  • No knowledge of SystemVerilog OOP (object oriented programming) required
  • No knowledge of SystemVerilog UVM (Universal Verification methodology) required
What you will learn
  • Get you up and running in the shortest possible time. No knowledge of SystemVerilog OOP or UVM required
  • Make you confident in spotting those critical and hard to find bugs
  • Easily grasp the concepts of multi-threading from a hardware designer perspective
  • This course will go step-by-step through each of SystemVerilog Assertions (SVA) language feature and methodology component with practical applications at each step
  • You will also get in-depth knowledge (from scratch) of SystemVerilog Functional Coverage Language, Methodology and Applications.
  • Be confident in applying for new jobs or projects knowing that you have in-depth knowledge of two of the most important subjects in Design Verification, namely SVA and FC
Number of Lectures: 22
Total Duration: 06:18:12
Welcome and introduction to SystemVerilog Assertions
  • Welcome and introduction to SystemVerilog Assertions  

    This lecture will provide an introduction to SystemVerilog Assertions, its evolution from PSL, Sugar, etc. and clearly outline course objectives

  • What is an Assertion? What are the benefits? Project wide methodology guidelines  

    We will discuss the basic definition of an Assertion. Its pros and cons and project wide methodology.

Immediate Assertions
  • Types of assertions, Immediate and Deferred immediate assertions  

    This lecture will introduce Immediate Assertions and Deferred Immediate Assertions

Concurrent Assertions – Basics
  • Sequence, Property, Assert and Cover. Implication Operator (Overlapping, Non-ove  

    This lecture will discuss in-depth the definitions of sequence, property, assert and cover. It will also discuss Implication Operators such as Overlapping and Non-overlapping. This lecture is foundation to the course.

  • Clocking basics (singly clocked properties)  

    This lecture will discuss how SystemVerilog Assertions are sampled in the pre-poned region of a clock edge. It will discuss nuances of singly clocked properties.

  • Multi-threading, Formal arguments, disable iff and severity levels  

    This lecture discusses the most fundamental semantic of the language - that being the concept of multi-threading and pipelined behavior. It then goes into the discussion of formal and actual arguments and their connectivity. other features discussed are assertion execution terminate system features such as 'disable iff'

  • Binding properties  

    SVA allows you to write properties / assertions for either VHDL or Verilog design. You write the assertions in SVA and 'bind' those to either VHDL or Verilog RTL.

Concurrent Assertions – Sampled Value Function
  • Sampled value Functions (PART 1): $rose, $fell  

    This lecture discusses the so-called Sampled Value Functions, namely $rose and $fell.

  • Sampled Value Functions (PART 2) : $stable, $past, $changed, $sampled  

    This lecture discusses Sampled Value Functions such as $past, $stable, $changed, $sampled, etc. It also discusses Global clocking PAST and FUTURE sampled value functions.

Concurrent Assertions – Operators
  • Clock delay operator  

    This lecture discusses fundamentals of Clock Delay and Clock Delay Range operators.

  • Consecutive Repetition  

    This lecture dives deep into the Consecutive Repetition Operator.

  • Non-consecutive repetition, Non-consecutive GoTo  

    This lecture dives deep into Non-Consecutive repetition and Non-Consecutive GOTO operators. Shows the similarity and differences between the two operators.

  • ‘throughout’, ‘within’  

    This lecture discusses the operators "throughout' and 'within'

  • ‘and’, ‘or’, ‘intersect’  

    This lecture discusses the operators 'and', 'or' and 'intersect' as applied to procedural code as well as concurrent assertion.

  • ‘first_match’, ‘if … else’, ‘iff’, ‘implies’  

    This lecture discusses the important concept of 'first_match' and its effective use in an Antecedent. It then follows with if-then-else, iff and 'implies' features.

System Functions and Tasks
  • $onehot, $onehot0, $isunknown, $countones and assertion execution control tasks  

    $onehot, $onehot0, $isunknown, $countones

    Assertion execution control tasks: $assertoff, $asserton, $assertkill, $assertpassoff, $assertpasson, $assertfailoff, $assertfailon, $assertnonvacuouson, $assertvacuousoff, $assertcontrol

Multiply clocked properties and sequences
  • Multiply clocked properties and sequences and operators 'and', 'or', etc.  

    16.Multiply clocked sequences. Multiply clocked properties: ‘and’, ‘or’, ‘not’ operators. Multiple Clock resolution

Local Variables and Endpoint sequence methods
  • Local Variables  

    This lectures dives deep into SystemVerilog Assertions (SVA) 'Local Variables'. Plenty of applications are given.

  • .triggered, .matched, Calling subroutines, sequence as a formal argument, sequen  
  • ‘expect’, ‘assume’ Blocking ‘action block’  

    This lecture discusses 'expect', 'assume', Blocking 'action block' etc. important features of SVA.

  • Asynchronous FIFO Assertions  

    This lecture shows how to write SVA assertion for an Asynchronous FIFO.

IEEE-1800: LRM 2009/2012 features
  • ‘let’ declarations and ‘checker’  

    This lecture discusses the IEEE-1800 LRM 2009 and 2012 features such as 'let declarations' and 'checker'

QUIZ 1: Synchronous FIFO QUIZ 2: Up-Down Counter
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