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SystemVerilog Functional Coverage Language/methodology/apps

Features Includes:
  • Self-paced with Life Time Access
  • Certificate on Completion
  • Access on Android and iOS App

Course Preview Video

  • Categories

    Blueprint & Designing

  • Duration

    01:39:03

  • 0 Students Enrolled

Description

The knowledge gained from this course will help you cover those critical and hard to find design bugs. SystemVerilog Functional Coverage Language and Methodology is a very important part of overall functional verification methodology and all verification engineers need this knowledge to be successful. The knowledge of FC will indeed be a highlight of your resume when seeking a challenging job or project The course offers step-by-step guide to learning of FC with real life applications to help you solidify your concepts and apply FC to your project in shortest possible time. FC helps the critical part of Functional/Temporal domain coverage which is simply not possible with code coverage.The course does not require any prior knowledge of SystemVerilog or OOP (Object oriented programming) or UVM. The course has 9 lectures that will take you step by step through FC language from scratch.

Who is the target audience?

  • Hardware design and verification engineers, Verification IP developers and EDA application engineers are best suited for this course
  • New college graduates will also benefit tremendously from this course

Basic knowledge
  • This course will go step-by-step through each of Functional Coverage (FC) language feature and methodology component with practical applications at each step - FROM SCRATCH
  • You only need very basic knowledge of hardware design and verification
  • You do NOT need knowledge of Object Oriented Programming (OOP) or Universal Verification Methodology (UVM)

What will you learn
  • Get you up and running in the shortest possible time. No knowledge of SystemVerilog OOP or UVM required
  • Make you confident in seeing that you have fully 'functionally' covered your design and testbench before tape-out
  • Make you knowledgeable in one of the most important and critical part of overall Design Verification landscape
  • Will make your resume even stronger in the competitive DV landscape
Course Curriculum
Number of Lectures: 9 Total Duration: 01:39:03
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